Reduced instruction set computers (RISC) recognize the advantages of using simple decoding and the pipelined execution of instructions. Branch instructions are required in a computer to control the flow of instructions. A branch instruction in a pipelined computer will normally delay the pipeline until the instruction at the location to which the branch instruction transferred control, the "branch address", is fetched. As such, these instructions impede the normal pipelined flow of instructions. Known in the prior art are elaborate techniques which delay the effect of branches, "delayed branching", or predicting branches ahead of time and correcting for wrong predictions, or fetching multiple instructions until the direction of the branch is known.
Since most of these techniques are too complex for a RISC architecture, the delayed branch is chosen for it; the delayed branch allows RISC to always fetch the (physically) next instruction during the execution of the current instruction. As most RISCs employ pipelining of instructions, in the prior art delayed branching requires two instruction processor clock cycles to execute a branch instruction. This disrupts the instruction pipeline. Complex circuitry was introduced into the prior art to eliminate such disruption. Since branch instructions occur frequently within the instruction stream, prior art computers were slower and more complex than desired.
Since calls on subroutines and interrupt and trap routines similarly involve branching, the time penalties incurred in the prior art RISCs are also present for these commonly-occurring procedures. Accordingly, there is a need for an instruction processor suitable for use in a RISC which performs branches in a single cycle, and thus does not disrupt the instruction pipeline, while providing completely accurate branch prediction without requiring complex circuitry.